LSCs: Breathing Life into Message Sequence Charts
Formal Methods in System Design
Formal Methods in Designing Embedded Systems—the SACRES Experience
Formal Methods in System Design
Verification of a Radio-Based Signaling System Using the STATEMATE Verification Environment
Formal Methods in System Design
An Automata Based Interpretation of Live Sequence Charts
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Efficient Decompositional Model Checking for Regular Timing Diagrams
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Embedded Systems: Challenges in Specification and Verification
EMSOFT '02 Proceedings of the Second International Conference on Embedded Software
Constructing Test Automata from Graphical Real-Time Requirements
FTRTFT '02 Proceedings of the 7th International Symposium on Formal Techniques in Real-Time and Fault-Tolerant Systems: Co-sponsored by IFIP WG 2.2
On the expressive power of live sequence charts
Program analysis and compilation, theory and practice
Verifying statemate statecharts using CSP and FDR
ICFEM'06 Proceedings of the 8th international conference on Formal Methods and Software Engineering
Visual temporal logic as a rapid prototyping tool
Computer Languages
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