Visual temporal logic as a rapid prototyping tool

  • Authors:
  • Martin FräNzle;Karsten LüTh

  • Affiliations:
  • Carl von Ossietzky Universität Oldenburg, Department of Computer Science, P.O. Box 2503, D-26111 Oldenburg, Germany;Carl von Ossietzky Universität Oldenburg, Department of Computer Science, P.O. Box 2503, D-26111 Oldenburg, Germany

  • Venue:
  • Computer Languages
  • Year:
  • 2001

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Abstract

Within this survey article, we explain real-time symbolic timing diagrams and the ICOS tool-box supporting timing-diagram-based requirements capture and rapid prototyping. Real-time symbolic timing diagrams are a full-fledged metric-time temporal logic, but with a graphical syntax reminiscent of the informal timing diagrams widely used in electrical engineering. ICOS integrates a variety of tools, ranging from graphical specification editors over tautology checking and counterexample generation to code generators emitting C or VHDL, thus bridging the gap from formal specification to rapid prototype generation.