Data structures and network algorithms
Data structures and network algorithms
An Algebraic Model for Asynchronous Circuits Verification
IEEE Transactions on Computers
Constraint satisfaction in logic programming
Constraint satisfaction in logic programming
Trace theory for automatic hierarchical verification of speed-independent circuits
Trace theory for automatic hierarchical verification of speed-independent circuits
Timing assumptions and verification of finite-state concurrent systems
Proceedings of the international workshop on Automatic verification methods for finite state systems
High level synthesis of ASICs under timing and synchronization constraints
High level synthesis of ASICs under timing and synchronization constraints
Constraint arithmetic on real intervals
Constraint logic programming
Model-checking in dense real-time
Information and Computation - Special issue: selections from 1990 IEEE symposium on logic in computer science
Theoretical Computer Science
Modeling and synthesis of timed asynchronous circuits
EURO-DAC '94 Proceedings of the conference on European design automation
Practical applications of an efficient time separation of events algorithm
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Min-max linear programming and the timing analysis of digital circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Logic Circuits and Microcomputer Systems
Logic Circuits and Microcomputer Systems
Algorithms for Interface Timing Verification
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Realizable and Unrealizable Specifications of Reactive Systems
ICALP '89 Proceedings of the 16th International Colloquium on Automata, Languages and Programming
Solving Linear, Min and Max Constraint Systems Using CLP based on Relational Interval Arithmetic
CP '95 Proceedings of the First International Conference on Principles and Practice of Constraint Programming
Integrating Behavior and Timing in Executable Specifications
CHDL '93 Proceedings of the 11th IFIP WG10.2 International Conference sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC on Computer Hardware Description Languages and their Applications
A new interface specification methodology and its application to transducer synthesis
A new interface specification methodology and its application to transducer synthesis
Synthesis and Optimization of Combinational Interface Circuits
Journal of VLSI Signal Processing Systems
Maximum Time Separation of Events in Cyclic Systems with Linear and Latest Timing Constraints
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Efficient Decompositional Model Checking for Regular Timing Diagrams
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Model Checking Synchronous Timing Diagrams
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Formal hardware specification languages for protocol compliance verification
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Reasoning about synchronization in GALS systems
Formal Methods in System Design
An evaluation of timed scenario notations
Journal of Systems and Software
Pattern synthesis from multiple scenarios for parameterized real-time UML models
SMTT'03 Proceedings of the 2003 international conference on Scenarios: models, Transformations and Tools
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Specifications containing linear timing constraints, such as found in action diagrams (timing diagrams) defining interface behaviors, are often used in practice. Although efficient O(n3) shortest path algorithms exist for computing the minimum and maximum time distances between actions, subject to the timing constraints, there is so far no accurate method that can decide (a) whether a specification of this kind is realizable (i.e., can be simulated by a causal system), and (b) given the action diagrams of the interfaces of two or more communicating systems, whether the systems implementing such independent specifications will correctly interoperate (i.e., satisfy the respective protocols and timing assumptions). First we illustrate the weakness of existing action diagram verification techniques: the causality issue is not addressed, and the proposed methods to answer the compatibility (interoperability) question yield false negative answers in many practical situations. We then define the meaning of causality in an action diagram specification and state a set of sufficient conditions for causality to hold. This development then leads to an exact procedure for the verification of the interface compatibility of communicating action diagrams. the results are illustrated on a practical example.