Pattern synthesis from multiple scenarios for parameterized real-time UML models

  • Authors:

  • Holger Giese;Florian Klein;Sven Burmester

  • Affiliations:

  • Software Engineering Group, University of Paderborn, Paderborn, Germany;Software Engineering Group, University of Paderborn, Paderborn, Germany;Software Engineering Group, University of Paderborn, Paderborn, Germany

  • Venue:
  • SMTT'03 Proceedings of the 2003 international conference on Scenarios: models, Transformations and Tools
  • Year:
  • 2003

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Abstract

The continuing trend towards more sophisticated technical applications results in an increasing demand for high quality software for complex, safety-critical systems. Designing and verifying the coordination between the components of such a system in order to ensure its overall correctness and safe operation are crucial and costly steps of the development process. In this paper, we extend our approach for the compositional formal verification of UML-RT models described by components and patterns [1], which addresses this challenge. We outline how scenario-based synthesis techniques can facilitate the design and verification steps by automatically deriving the required pattern behavior. Starting from a set of timed scenarios, the presented procedure generates a set of statecharts with additional real-time annotations that realize these scenarios. As parameterized timed scenarios are supported, different system configurations can be specified as required by adjusting the behavior using the specific timing constraints. The paper describes the proposed approach using a running example and presents first results obtained using a prototype implementation.