VERIFY: a program for proving correctness of digital hardware designs
Artificial Intelligence - Special volume on qualitative reasoning about physical systems
Lattice functions and equations
Lattice functions and equations
Asynchronous Sequential Switching Circuit
Asynchronous Sequential Switching Circuit
Switching and Finite Automata Theory: Computer Science Series
Switching and Finite Automata Theory: Computer Science Series
Introduction to VLSI Systems
Automated Reasoning: Introduction and Applications
Automated Reasoning: Introduction and Applications
A model for hardware description and verification
DAC '84 Proceedings of the 21st Design Automation Conference
A formal design verification system based on an automated reasoning system
DAC '84 Proceedings of the 21st Design Automation Conference
Hardware verification.
Functional Description of Connector-Switch-Attenuator Networks
IEEE Transactions on Computers
ACM Transactions on Programming Languages and Systems (TOPLAS)
Semantics and verification of action diagrams with linear timing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
| Hi-index | 14.98 |
An algebraic methodology for comparing switch-level circuits with higher-level specifications is presented. Switch-level networks, 'user' behavior, and input constraints are modeled as asynchronous machines. The model is based on the algebraic theory of characteristic functions (CF). An asynchronous automation is represented by a pair of CFs, called a dynamic CF (DCF): the first CF describes the potential stable states, and the second CF describes the possible transitions. The set of DCFs is a Boolean algebra. Machine composition and internal variables abstraction correspond, respectively, to the product and sum operations of the algebra. Internal variables can be abstracted under the presence of a domain constraint. The constraint is validated by comparison to the outside behavior. The model is well suited for speed-independent circuits for which the specification is given as a collection of properties. Verification reduces to the validation of Boolean inequalities.