The FSM network model for behavioral synthesis of control-dominated machines
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
OEsim: a simulator for timing behavior
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
The automatic generation of bus-interface models
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Synthesis of concurrent system interface modules with automatic protocol conversion generation
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Modeling and synthesis of timed asynchronous circuits
EURO-DAC '94 Proceedings of the conference on European design automation
Interfacing incompatible protocols using interface process generation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
An approach to guided incremental specification
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
An algorithm for synthesis of system-level interface circuits
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Symbolic timing verification of timing diagrams using Presburger formulas
DAC '97 Proceedings of the 34th annual Design Automation Conference
Semantics and verification of action diagrams with linear timing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Automatic synthesis of interfaces between incompatible protocols
DAC '98 Proceedings of the 35th annual Design Automation Conference
On Deducing Timing Constraints in the Verification of Interfaces
Formal Methods in System Design
Forced simulation: A technique for automating component reuse in embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Synthesis and Optimization of Combinational Interface Circuits
Journal of VLSI Signal Processing Systems
Scheduling for Reactive Real-Time Systems
IEEE Micro
An Algorithm for Exact Bounds on the Time Separation of Events in Concurrent Systems
IEEE Transactions on Computers
An Object-Oriented Communication Library for Hardware-Software CoDesign
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Min-Max Inequalities and the Timing Verification Problem with Max and Linear Constraints
Discrete Event Dynamic Systems
Towards a synthesis semantics for systemC channels
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
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