Synthesis of concurrent system interface modules with automatic protocol conversion generation
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Interface timing verification with application to synthesis
DAC '94 Proceedings of the 31st annual Design Automation Conference
Interfacing incompatible protocols using interface process generation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Interface co-synthesis techniques for embedded systems
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Design of system interface modules
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Synthesis fo the hardware/software interface in microcontroller-based systems
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
A new interface specification methodology and its application to transducer synthesis
A new interface specification methodology and its application to transducer synthesis
Exploiting intellectual properties in ASIP designs for embedded DSP software
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
FRONTIERS '96 Proceedings of the 6th Symposium on the Frontiers of Massively Parallel Computation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A UML-based approach for heterogeneous IP integration
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
| Hi-index | 0.00 |
We describe an algorithm for the synthesis and optimization of interface circuits for embedded system components such as microprocessors, memory ASIC, and network subsystems with fixed interfaces. The algorithm accepts the timing characteristics of two system components as input, and generates a combinational interface (glue logic) circuit. The algorithm consists of two parts. In the first part, we determine the direct pin-to-pin connections in the interface circuit employing a 0/1 ILP formulation to minimize wiring area and dynamic power consumption. In the second part, we determine logic subcircuits in the interface circuit, utilizing the timing diagrams of the system components. The proposed algorithm has been implemented in a software package SYNTERFACE. Experimental results are presented to demonstrate the effectiveness of the algorithm.