Interfacing incompatible protocols using interface process generation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
An algorithm for synthesis of system-level interface circuits
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Protocol selection and interface generation for HW-SW codesign
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automated composition of hardware components
DAC '98 Proceedings of the 35th annual Design Automation Conference
Design of system interface modules
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
ipChinook: an integrated IP-based design framework for distributed embedded systems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Exploiting intellectual properties in ASIP designs for embedded DSP software
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Models and methods for HW/SW intellectual property interfacing
System-level synthesis
Design methodologies for system level IP
Proceedings of the conference on Design, automation and test in Europe
Embedded tutorial: essential issues for IP reuse
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Component-based design approach for multicore SoCs
Proceedings of the 39th annual Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Interface co-synthesis techniques for embedded systems
Readings in hardware/software co-design
Exploiting intellectual properties with imprecise design costs for system-on-chip synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Introducing Core-Based System Design
IEEE Design & Test
Specification, Modeling and Design Tools for System-on-Chip
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Benefits and challenges for platform-based design
Proceedings of the 41st annual Design Automation Conference
Facilitating Reuse in Hardware Models with Enhanced Type Inference
CODES+ISSS '04 Proceedings of the international conference on Hardware/Software Codesign and System Synthesis: 2004
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Resource budgeting for Multiprocess High-level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The Intellectual Property (IP)-based design for high-throughput dedicated digital signal processing (DSP) systems is obviously an important issue for improving not only design productivity, but also design from the high level of abstraction. However, in some cases, synthesizable register transfer level (RTL) model obtained by an automatic assembly of RTL IPs can be wrong due to delays induced by implementation constraints. In this paper, we present the formalization of the problem and propose an approach called automatic delay correction method (ADCM) to solve the problem without inserting an extra interface circuitry. The approach automatically inserts control structures to manage delays induced by the use of RTL IPs. It also inserts a control structure to coordinate the execution of parallel clocked IPs. The delays may be managed by registers or by counters included in the control structure. A formal theory of ADCM is developed to guide the implementation and guarantee optimal solutions in latency and area. Through experiments with synthetic example and three real world high-throughput DSP circuits, we also show the effectiveness of our approach.