Setting up a retrieval system for design reuse—experiences and acceptance
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Reuse methodology manual: for system-on-a-chip designs
Reuse methodology manual: for system-on-a-chip designs
Design of system interface modules
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
MOCSYN: multiobjective core-based single-chip system synthesis
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Exploiting intellectual properties in ASIP designs for embedded DSP software
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Design methodologies for system level IP
Proceedings of the conference on Design, automation and test in Europe
Component-based design approach for multicore SoCs
Proceedings of the 39th annual Design Automation Conference
Exploiting intellectual properties with imprecise design costs for system-on-chip synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Introducing Core-Based System Design
IEEE Design & Test
Colif: A Design Representation for Application-Specific Multiprocessor SOCs
IEEE Design & Test
Framework for System Design, Validation and Fast Prototyping of Multiprocessor System-On-Chip
DIPES '00 Proceedings of the IFIP WG10.3/WG10.4/WG10.5 International Workshop on Distributed and Parallel Embedded Systems: Architecture and Design of Distributed Embedded Systems
RSP '03 Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP'03)
RSP '01 Proceedings of the 12th International Workshop on Rapid System Prototyping
Journal of Systems and Software - Special issue: Rapid system prototyping
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The Growing requirement on the correct design of a high performance DSP system in short time force us to use IP's in many design. In this paper, we propose an efficient IP block based design environment for high throughput VLSI Systems. The flow generates SystemC Register Transfer Level (RTL) architecture, starting from a Matlab functional model described as a netlist of functional IP. The refinement process inserts automatically control structures to treat delays induced by the use of RTL IPs. It also inserts a control structure to coordinate the execution of parallel clocked IP. The delays may be managed by registers or by counters included in the control structure. The experimentations show that the approach can produce efficient RTL architecture and allow a huge save of time.