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EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Protocol selection and interface generation for HW-SW codesign
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Core integration: overview and challenges
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Improving the computational performance of ILP-based problems
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Fuzzy logic: intelligence, control, and information
Fuzzy logic: intelligence, control, and information
COSYN: hardware-software co-synthesis of heterogeneous distributed embedded systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
MOCSYN: multiobjective core-based single-chip system synthesis
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Exploiting intellectual properties in ASIP designs for embedded DSP software
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
IEEE Spectrum
Surviving the SOC revolution: a guide to platform-based design
Surviving the SOC revolution: a guide to platform-based design
Fuzzy Sets and Systems - Fuzzy mathematical programming
Design methodologies for system level IP
Proceedings of the conference on Design, automation and test in Europe
How VSIA Answers the SOC Dilemma
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Proceedings of the 19th IFIP TC7 Conference on System Modelling and Optimization: Methods, Theory and Applications
Hardware/Software Partitioning using Integer Programming
EDTC '96 Proceedings of the 1996 European conference on Design and Test
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ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
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ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
A common transform engine for MPEG and AC3 audio decoder
IEEE Transactions on Consumer Electronics
A low-power MPEG audio layer III decoder IC with an integrated digital-to-analog converter
IEEE Transactions on Consumer Electronics
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
EURASIP Journal on Applied Signal Processing
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This paper presents an intellectual property (IP)-based system-on-chip (SoC) synthesis framework focusing on how to select IPs from different sources and how to integrate the selected IPs using on-chip buses. In order to synthesize an on-chip bus-based SoC architecture using IPs with imprecise design costs, we propose a possibilistic mixed integer linear programming (PMILP) model, which is converted into an equivalent mixed integer linear programming (MILP) model without increasing the computational complexity. Then, the equivalent MILP model is solved to decide whether each IP is selected or not, and to locate the selected IP on the optimal on-chip bus of a hierarchical bus architecture that consists of on-chip buses with different bus attributes. Experimental results on an MP3 decoding system show that the IP-centric design space with uncertainty can be successfully explored using the proposed scheme.