Hardware-software co-design of embedded systems: the POLIS approach
Hardware-software co-design of embedded systems: the POLIS approach
Automatic synthesis of interfaces between incompatible protocols
DAC '98 Proceedings of the 35th annual Design Automation Conference
Hardware synthesis from C/C++ models
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Exploiting intellectual properties in ASIP designs for embedded DSP software
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Design methodologies for system level IP
Proceedings of the conference on Design, automation and test in Europe
Embedded tutorial: essential issues for IP reuse
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Component-based design approach for multicore SoCs
Proceedings of the 39th annual Design Automation Conference
Exploiting intellectual properties with imprecise design costs for system-on-chip synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Introducing Core-Based System Design
IEEE Design & Test
Colif: A Design Representation for Application-Specific Multiprocessor SOCs
IEEE Design & Test
Specification, Modeling and Design Tools for System-on-Chip
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
HardwareC -- A Language for Hardware Design (Version 2.0)
HardwareC -- A Language for Hardware Design (Version 2.0)
Benefits and challenges for platform-based design
Proceedings of the 41st annual Design Automation Conference
Facilitating reuse in hardware models with enhanced type inference
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
The Challenges of Hardware Synthesis from C-Like Languages
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Logic foundry: rapid prototyping for FPGA-based DSP systems
EURASIP Journal on Applied Signal Processing
Accurate Area, Time and Power Models for FPGA-Based Implementations
Journal of Signal Processing Systems
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We propose an efficient IP-block-based design environment for high-throughput VLSI systems. The flow generates SystemC register-transfer-level (RTL) architecture, starting from a Matlab functional model described as a netlist of functional IP. The refinement model inserts automatically control structures to manage delays induced by the use of RTL IPs. It also inserts a control structure to coordinate the execution of parallel clocked IP. The delays may be managed by registers or by counters included in the control structure. The flow has been used successfully in three real-world DSP systems. The experimentations show that the approach can produce efficient RTL architecture and allows to save huge amount of time.