Design of a processing board for a programmable multi-VSP system
Journal of VLSI Signal Processing Systems - Special issue: video/image signal processing
Consistency in Dataflow Graphs
IEEE Transactions on Parallel and Distributed Systems
A preliminary architecture for a basic data-flow processor
ISCA '75 Proceedings of the 2nd annual symposium on Computer architecture
DAC '96 Proceedings of the 33rd annual Design Automation Conference
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A strategy for real-time kernel support in application-specific HW/SW embedded architectures
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A system level HW/SW partitioning and optimization tool
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Prototyping of the receiver unit for a broadband access network
ISSS '97 Proceedings of the 10th international symposium on System synthesis
Data memory minimisation for synchronous data flow graphs emulated on DSP-FPGA targets
DAC '97 Proceedings of the 34th annual Design Automation Conference
A programming environment for the design of complex high speed ASICs
DAC '98 Proceedings of the 35th annual Design Automation Conference
A path analysis based partitioning for time constrained embedded systems
Proceedings of the 6th international workshop on Hardware/software codesign
Implementation of Hard Real-Time Embedded Control Systems
Real-Time Systems
Matisse: A System-on-Chip Design Methodology Emphasizing Dynamic Memory Management
Journal of VLSI Signal Processing Systems - Special issue on system level design
A dataflow specification for system level synthesis of 3D graphics applications
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Efficient hardware controller synthesis for synchronous dataflow graph in system level design
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Hardware synthesis from SPDF representation for multimedia applications
ISSS '00 Proceedings of the 13th international symposium on System synthesis
The Implementation of Synchronous Dataflow Graphs Using Reconfigurable Hardware
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Efficient hardware controller synthesis for synchronous dataflow graph in system level design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Synthesis of multi-rate and variable rate circuits for high speed telecommunications applications
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Implementing DSP applications on heterogeneous targets using minimal size data buffers
RSP '96 Proceedings of the 7th IEEE International Workshop on Rapid System Prototyping (RSP '96)
Data Routing in Dataflow Graphs
RSP '97 Proceedings of the 8th International Workshop on Rapid System Prototyping (RSP '97) Shortening the Path from Specification to Prototype
Rapid Prototyping of Communication Architectures
RSP '97 Proceedings of the 8th International Workshop on Rapid System Prototyping (RSP '97) Shortening the Path from Specification to Prototype
Task-level timing models for guaranteed performance in multiprocessor networks-on-chip
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Rapid Prototyping of Flexible Embedded Systems on Multi-DSP Architectures
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Logic foundry: rapid prototyping of FPGA-based DSP systems
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
A methodology to implement real-time applications onto reconfigurable circuits
The Journal of Supercomputing
Multidimensional DSP Core Synthesis for FPGA
Journal of VLSI Signal Processing Systems
Software synthesis from the dataflow interchange format
SCOPES '05 Proceedings of the 2005 workshop on Software and compilers for embedded systems
Journal of Systems and Software
Efficient simulation of critical synchronous dataflow graphs
Proceedings of the 43rd annual Design Automation Conference
Compiling concurrent programs for embedded sequential execution
Integration, the VLSI Journal
Beyond single-appearance schedules: Efficient DSP software synthesis using nested procedure calls
ACM Transactions on Embedded Computing Systems (TECS) - SPECIAL ISSUE SCOPES 2005
Rapid implementation and optimisation of DSP systems on FPGA-centric heterogeneous platforms
Journal of Systems Architecture: the EUROMICRO Journal
Efficient simulation of critical synchronous dataflow graphs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Flexible Controller Design and Its Application for Concurrent Execution of Buffer Centric Dataflows
Journal of VLSI Signal Processing Systems
Simplifying physical realization of Gaussian particle filters with block-level pipeline control
EURASIP Journal on Applied Signal Processing
EURASIP Journal on Embedded Systems
EURASIP Journal on Applied Signal Processing
Optimized RTL Code Generation from Coarse-Grain Dataflow Specification for Fast HW/SW Cosynthesis
Journal of Signal Processing Systems
MPEG-2 decoding in a stream programming language
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Correct and non-defensive glue design using abstract models
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Rapid implementation and optimisation of DSP systems on SoPC heterogeneous platforms
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Static dataflow with access patterns: semantics and analysis
Proceedings of the 49th Annual Design Automation Conference
| Hi-index | 4.10 |
Grape-II (Graphical Rapid Prototyping Environment) is an advanced system-level development environment for specifying, compiling, debugging, simulating, and emulating digital-signal-processing applications. Its structured prototyping methodology reduces programming effort, and its use of general-purpose reusable hardware minimizes development cost. The general-purpose hardware consists of commercial DSP processors, bond-out versions of core processors, and FPGAs linked to form a powerful, heterogeneous multiprocessor, such as the Paradigm RP developed within the Retides (Real-Time DSP Emulation System) Esprit project and marketed by InCA/Zycad. Grape-II automates the prototyping methodology for these systems by offering tools for resource estimation, partitioning, assignment, routing, scheduling, code generation, and parameter modification. This prototyping approach has been successfully used for an audio processor for the consumer market, for a sender, receiver and channel simulator for digital audio broadcasting, and for a real- time video encoder for mobile applications. The video-encoder case study, described in the article, resulted in a full-speed operational prototype. This and other successes demonstrate the feasibility of the authors' strategy for prototyping real-time color video compression on a commercial DSP multiprocessor.