Implementing DSP applications on heterogeneous targets using minimal size data buffers

Authors:
M. Ade;R. Lauwereins;J. A. Peperstrate
Affiliations:
-;-;-
Venue:
RSP '96 Proceedings of the 7th IEEE International Workshop on Rapid System Prototyping (RSP '96)
Year:
1996

Citing 6
Cited 3

Static scheduling of synchronous data flow programs for digital signal processing

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Grape-II: A System-Level Prototyping Environment for DSP Applications

Computer
Consistency in Dataflow Graphs

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Converting graphical DSP programs into memory constrained software prototypes

RSP '95 Proceedings of the Sixth IEEE International Workshop on Rapid System Prototyping (RSP'95)
Hardware-software codesign with GRAPE

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Cycle-static dataflow

IEEE Transactions on Signal Processing

Memory efficient software synthesis form dataflow graph

Proceedings of the 11th international symposium on System synthesis
Data Routing in Dataflow Graphs

RSP '97 Proceedings of the 8th International Workshop on Rapid System Prototyping (RSP '97) Shortening the Path from Specification to Prototype
Buffer merging—a powerful technique for reducing memory requirements of synchronous dataflow specifications

ACM Transactions on Design Automation of Electronic Systems (TODAES)

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Abstract

The paper presents an algorithm to determine the smallest possible data buffer sizes for arbitrary synchronous data flow (SDF) applications, such that we can guarantee the existence of a deadlock free schedule. The presented algorithm fits in the design flow of GRAPE, an environment for the emulation and implementation of digital signal processing (DSP) systems on arbitrary target architectures, consisting of programmable DSP processors and FPGAs. Reducing the size of data buffers is of high importance when the application will be mapped on Field Programmable Gate Arrays (FPGA), since register resources are rather scarce.