Joint Minimization of Code and Data for Synchronous DataflowPrograms
Formal Methods in System Design
Data memory minimisation for synchronous data flow graphs emulated on DSP-FPGA targets
DAC '97 Proceedings of the 34th annual Design Automation Conference
Heterogeneous modeling and simulation of embedded systems in El Greco
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Code Generation for Embedded Processors
Code Generation for Embedded Processors
Software Synthesis from Dataflow Graphs
Software Synthesis from Dataflow Graphs
Introduction to Algorithms
Minimal Memory Schedules for Dataflow Networks
CONCUR '93 Proceedings of the 4th International Conference on Concurrency Theory
Scheduling dynamic dataflow graphs with bounded memory using the token flow model
Scheduling dynamic dataflow graphs with bounded memory using the token flow model
System Design Using Kahn Process Networks: The Compaan/Laura Approach
Proceedings of the conference on Design, automation and test in Europe - Volume 1
SystemC Kernel Extensions For Heterogenous System Modeling: A Framework for Multi-MoC Modeling & Simulation
Minimising buffer requirements of synchronous dataflow graphs with model checking
Proceedings of the 42nd annual Design Automation Conference
Memory optimal single appearance schedule with dynamic loop count for synchronous dataflow graphs
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Software synthesis from the dataflow interchange format
SCOPES '05 Proceedings of the 2005 workshop on Software and compilers for embedded systems
Efficient simulation of critical synchronous dataflow graphs
Proceedings of the 43rd annual Design Automation Conference
Memory Management for Synthesis of DSP Software
Memory Management for Synthesis of DSP Software
IEEE Transactions on Signal Processing
Multithreaded simulation for synchronous dataflow graphs
Proceedings of the 45th annual Design Automation Conference
Multithreaded Simulation for Synchronous Dataflow Graphs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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System-level modeling, simulation, and synthesis using electronic design automation (EDA) tools are key steps in the design process for communication and signal processing systems, and the synchronous dataflow (SDF) model of computation is widely used in EDA tools for these purposes. Behavioral representations of modern wireless communication systems typically result in critical SDF graphs: These consist of hundreds of components (or more) and involve complex intercomponent connections with highly multirate relationships (i.e., with large variations in average rates of data transfer or component execution across different subsystems). Simulating such systems using conventional SDF scheduling techniques generally leads to unacceptable simulation time and memory requirements on modern workstations and high-end PCs. In this article, we present a novel simulation-oriented scheduler (SOS) that strategically integrates several techniques for graph decomposition and SDF scheduling to provide effective, joint minimization of time and memory requirements for simulating critical SDF graphs. We have implemented SOS in the advanced design system (ADS) from Agilent Technologies. Our results from this implementation demonstrate large improvements in simulating real-world, large-scale, and highly multirate wireless communication systems (e.g., 3GPP, Bluetooth, 802.16e, CDMA 2000, XM radio, EDGE, and Digital TV).