Joint Minimization of Code and Data for Synchronous DataflowPrograms
Formal Methods in System Design
Data memory minimisation for synchronous data flow graphs emulated on DSP-FPGA targets
DAC '97 Proceedings of the 34th annual Design Automation Conference
Heterogeneous modeling and simulation of embedded systems in El Greco
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Code Generation for Embedded Processors
Code Generation for Embedded Processors
Software Synthesis from Dataflow Graphs
Software Synthesis from Dataflow Graphs
Scheduling dynamic dataflow graphs with bounded memory using the token flow model
Scheduling dynamic dataflow graphs with bounded memory using the token flow model
System Design Using Kahn Process Networks: The Compaan/Laura Approach
Proceedings of the conference on Design, automation and test in Europe - Volume 1
SystemC Kernel Extensions For Heterogenous System Modeling: A Framework for Multi-MoC Modeling & Simulation
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
Efficient simulation of critical synchronous dataflow graphs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A SystemC-based design methodology for digital signal processing systems
EURASIP Journal on Embedded Systems
Multithreaded simulation for synchronous dataflow graphs
Proceedings of the 45th annual Design Automation Conference
A mixed-mode vector-based dataflow approach for modeling and simulating LTE physical layer
Proceedings of the 47th Design Automation Conference
Emulating and diagnosing IR-drop by using dynamic SDF
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Multithreaded Simulation for Synchronous Dataflow Graphs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Topological Patterns for Scalable Representation and Analysis of Dataflow Graphs
Journal of Signal Processing Systems
Mapping Parameterized Cyclo-static Dataflow Graphs onto Configurable Hardware
Journal of Signal Processing Systems
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Simulation and verification using electronic design automation (EDA) tools are key steps in the design process for communication and signal processing systems. The synchronous dataflow (SDF) model of computation is widely used in EDA tools for system modeling and simulation in the communication and signal processing domains. Behavioral representations of practical wireless communication systems typically result in critical SDF graphs - they consist of hundreds of components (or more) and involve complex inter-component connections with highly multirate relationships (i.e., with large variations in average rates of data transfer or component execution across different subsystems). Simulating such systems using conventional SDF scheduling techniques generally leads to unacceptable simulation time and memory requirements on modern workstations and high-end PCs. In this paper, we present a novel simulation-oriented SDF scheduler (SOS) that strategically integrates several techniques for graph decomposition and SDF scheduling to provide effective, joint minimization of time and memory requirements for simulating large-scale and heavily multirate SDF graphs. We have implemented the SOS scheduler in the Advanced Design System (ADS) from Agilent Technologies. Our results from this implementation demonstrate large improvements in simulating real-world wireless communication systems (e.g. 3GPP, Bluetooth, 802.16e, CDMA 2000, and XM radio).