Topological Patterns for Scalable Representation and Analysis of Dataflow Graphs

  • Authors:

  • Nimish Sane;Hojin Kee;Gunasekaran Seetharaman;Shuvra S. Bhattacharyya

  • Affiliations:

  • Department of Electrical and Computer Engineering, and Institute for Advanced Computer Studies, University of Maryland, College Park, USA 20742;National Instruments, Austin, USA 78759;Air Force Research Laboratory, Rome, USA;Department of Electrical and Computer Engineering, and Institute for Advanced Computer Studies, University of Maryland, College Park, USA 20742

  • Venue:
  • Journal of Signal Processing Systems
  • Year:
  • 2011

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Abstract

Tools for designing signal processing systems with their semantic foundation in dataflow modeling often use high-level graphical user interfaces (GUIs) or text based languages that allow specifying applications as directed graphs. Such graphical representations serve as an initial reference point for further analysis and optimizations that lead to platform-specific implementations. For large-scale applications, the underlying graphs often consist of smaller substructures that repeat multiple times. To enable more concise representation and direct analysis of such substructures in the context of high level DSP specification languages and design tools, we develop the modeling concept of topological patterns, and propose ways for supporting this concept in a high-level language. We augment the dataflow interchange format (DIF) language--a language for specifying DSP-oriented dataflow graphs--with constructs for supporting topological patterns, and we show how topological patterns can be effective in various aspects of embedded signal processing design flows using specific application examples.