Consistency Analysis of Reconfigurable Dataflow Specifications
Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS
Consistency analysis of reconfigurable dataflow specifications
Embedded processor design challenges
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ACM Transactions on Embedded Computing Systems (TECS)
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Journal of Signal Processing Systems
Euro-Par'06 Proceedings of the 12th international conference on Parallel Processing
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DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Dataflow has proven to be an attractive computation model for programming DSP applications. A restricted version of dataflow, termed synchronous dataflow (SDF), that offers strong compile-time predictability properties, but has limited expressive power, has been studied extensively in the DSP context. Many extensions to synchronous dataflow have been proposed to increase its expressivity, while maintaining its compile-time predictability properties as much as possible. We propose a parameterized data-flow framework that can be applied as a meta-modeling technique to significantly improve the expressive power of an arbitrary data-flow model that possesses a well-defined concept of a graph iteration. Indeed, the parameterized dataflow framework is compatible with many of the existing dataflow models for DSP including SDF, CSDF, and SSDF. We develop a precise, formal semantics for parameterized synchronous dataflow that allows data-dependent dynamic DSP systems to be modeled in a natural and intuitive fashion. Desirable properties of a modeling environment like dynamic re-configurability and design re-use emerge as inherent characteristics of the parameterized framework. An example of a speech compression application is used to illustrate the efficacy of the parameterized modeling techniques in real-life data-dependent DSP systems.