FPGA implementation of a prototype hierarchical control network for large-scale signal processing applications

Authors:
Jérôme Lemaitre;Ed Deprettere
Affiliations:
ASTRON, Dwingeloo, The Netherlands;LIACS, Leiden university, Leiden, The Netherlands
Venue:
Euro-Par'06 Proceedings of the 12th international conference on Parallel Processing
Year:
2006

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Abstract

The performance of a high throughput and large-scale signal processing system must not be compromised by the control and monitoring flow that is inherently part of the system. In particular, the interfacing of data flow and control flow components should be such that control does not obstruct the signal flow that is of higher priority. We assume that the signal processing is modeled as a distributed hierarchy of data flow networks, and that the control and monitoring is modeled as a distributed hierarchy of communicating Finite State Machines. The interfaces between leaf-nodes of the control and monitoring network, and the signal processing nodes in the dataflow networks are specified in such a way that the semantics of both network types are preserved. In this paper, we present the prototyping of a control network and its interfacing with a data flow network in a FPGA-based platform, and we analyze the performance of the interfacing in a case study. The HDL code that is involved in the interfaces is generated in a semi-automated way.