FunState—an internal design representation for codesign

Authors:
Karsten Strehl;Lothar Thiele;Matthias Gries;Dirk Ziegenbein;Rolf Ernst;Jürgen Teich
Affiliations:
Research and Development, ETAS Stuttgart, Germany;Swiss Federal Institute of Technology, Zurich, Swizterland;Swiss Federal Institute of Technology, Zurich, Swizterland;Technical Univ. of Braunschweig, Braunschweig, Germany;Technical Univ. of Braunschweig, Braunschweig, Germany;Univ. of Paderborn, Paderborn, Germany
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2001

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Abstract

In this paper, an internal design model called FunState (functions driven by state machines) is presented that enables the representation of different types of system components and scheduling mechanisms using a mixture of functional programming and state machines. It is shown how properties relevant for scheduling and verification of specification models such as Boolean dataflow, cyclostatic dataflow, synchronous dataflow, marked graphs, and communicating state machines as well as Petri nets can be represented in the FunState model of computation. Examples of methods suited for FunState are described, such as scheduling and verification. They are based on the representation of the model's state transitions in the form of a periodic graph. The feasibility of the novel approach is shown with an asynchronous transfer mode switch example.