Scheduling synchronous dataflow graphs for efficient looping
Journal of VLSI Signal Processing Systems
Heterogeneous modeling and simulation of embedded systems in El Greco
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
YAPI: application modeling for signal processing systems
Proceedings of the 37th Annual Design Automation Conference
FunState—an internal design representation for codesign
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System Design with SystemC
Quasi-Static Scheduling of Embedded Software Using Equal Conflict Nets
Proceedings of the 20th International Conference on Application and Theory of Petri Nets
SPI: a system model for heterogeneously specified embedded systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Hierarchical Multiprocessor Scheduling System for DSP Applications
ASILOMAR '95 Proceedings of the 29th Asilomar Conference on Signals, Systems and Computers (2-Volume Set)
Software synthesis for dynamic data flow graph
RSP '97 Proceedings of the 8th International Workshop on Rapid System Prototyping (RSP '97) Shortening the Path from Specification to Prototype
Scheduling dynamic dataflow graphs with bounded memory using the token flow model
Scheduling dynamic dataflow graphs with bounded memory using the token flow model
Proceedings of the 4th ACM international conference on Embedded software
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
SHIM: a deterministic model for heterogeneous embedded systems
Proceedings of the 5th ACM international conference on Embedded software
Software synthesis from the dataflow interchange format
SCOPES '05 Proceedings of the 2005 workshop on Software and compilers for embedded systems
Programming models and HW-SW interfaces abstraction for multi-processor SoC
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the 43rd annual Design Automation Conference
UML-based multiprocessor SoC design framework
ACM Transactions on Embedded Computing Systems (TECS)
ACSD '06 Proceedings of the Sixth International Conference on Application of Concurrency to System Design
Efficient Techniques for Clustering and Scheduling onto Embedded Multiprocessors
IEEE Transactions on Parallel and Distributed Systems
Parameterized dataflow modeling of DSP systems
ICASSP '00 Proceedings of the Acoustics, Speech, and Signal Processing, 2000. on IEEE International Conference - Volume 06
Efficient computation of buffer capacities for cyclo-static dataflow graphs
Proceedings of the 44th annual Design Automation Conference
A framework for rapid system-level exploration, synthesis, and programming of multimedia MP-SoCs
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
A generalized static data flow clustering algorithm for mpsoc scheduling of multimedia applications
EMSOFT '08 Proceedings of the 8th ACM international conference on Embedded software
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IEEE Transactions on Signal Processing
A framework for comparing models of computation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hi-index | 0.00 |
Applications in the signal processing domain are often modeled by dataflow graphs. Due to heterogeneous complexity requirements, these graphs contain both dynamic and static dataflow actors. In previous work, we presented a generalized clustering approach for these heterogeneous dataflow graphs in the presence of unbounded buffers. This clustering approach allows the application of static scheduling methodologies for static parts of an application during embedded software generation for multiprocessor systems. It systematically exploits the predictability and efficiency of the static dataflow model to obtain latency and throughput improvements. In this article, we present a generalization of this clustering technique to dataflow graphs with bounded buffers, therefore enabling synthesis for embedded systems without dynamic memory allocation. Furthermore, a case study is given to demonstrate the performance benefits of the approach.