Heterogeneous behavioral hierarchy for system level designs
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A smooth refinement flow for co-designing HW and SW threads
Proceedings of the conference on Design, automation and test in Europe
A SystemC-based design methodology for digital signal processing systems
EURASIP Journal on Embedded Systems
A novel approach to entirely integrate virtual test into test development flow
Proceedings of the Conference on Design, Automation and Test in Europe
SC-DEVS: an efficient SystemC extension for the DEVS model of computation
Proceedings of the Conference on Design, Automation and Test in Europe
Analysis of SystemC actor networks for efficient synthesis
ACM Transactions on Embedded Computing Systems (TECS)
SCGPSim: a fast SystemC simulator on GPUs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
A fast heuristic scheduling algorithm for periodic ConcurrenC models
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Accelerating UNISIM-Based Cycle-Level Microarchitectural Simulations on Multicore Platforms
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Integration of Dataflow-Based Heterogeneous Multiprocessor Scheduling Techniques in GNU Radio
Journal of Signal Processing Systems
A model reduction approach for improving discrete event simulation performance
Proceedings of the 6th International ICST Conference on Simulation Tools and Techniques
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As SystemC gains popularity as a modeling language of choice for system-on-chip (SoC) designs, heterogeneous modeling in SystemC and efficient simulation become increasingly important. However, in the current reference implementation, all SystemC models are simulated through a nondeterministic discrete-event (DE) simulation kernel that schedules events at run time mimicking other models of computation (MoCs) using DE, which may get cumbersome. This sometimes results in too many delta cycles hindering the simulation performance of the model. SystemC also uses this simulation kernel as the target simulation engine. This makes it difficult to express different MoCs naturally in SystemC. In an SoC model, different components may need to be naturally expressible in different MoCs. These components may be amenable to static scheduling-based simulation or other presimulation optimization techniques. The goal is to create a simulation framework for heterogeneous SystemC models and to gain efficiency and ease of use within the framework of SystemC reference implementation. In this paper, a synchronous data flow (SDF) kernel extension for SystemC is introduced. Experimental results showing improvement in simulation time are also presented.