UML-based multiprocessor SoC design framework

  • Authors:

  • Tero Kangas;Petri Kukkala;Heikki Orsila;Erno Salminen;Marko Hännikäinen;Timo D. Hämäläinen;Jouni Riihimäki;Kimmo Kuusilinna

  • Affiliations:

  • Tampere University of Technology, Tampere, Finland;Tampere University of Technology, Tampere, Finland;Tampere University of Technology, Tampere, Finland;Tampere University of Technology, Tampere, Finland;Tampere University of Technology, Tampere, Finland;Tampere University of Technology, Tampere, Finland;Nokia Technology Platforms, Tampere, Finland;Nokia Research Center, Tampere, Finland

  • Venue:
  • ACM Transactions on Embedded Computing Systems (TECS)
  • Year:
  • 2006

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Abstract

This paper describes a complete design flow for multiprocessor systems-on-chips (SoCs) covering the design phases from system-level modeling to FPGA prototyping. The design of complex heterogeneous systems is enabled by raising the abstraction level and providing several system-level design automation tools. The system is modeled in a UML design environment following a new UML profile that specifies the practices for orthogonal application and architecture modeling. The design flow tools are governed in a single framework that combines the subtools into a seamless flow and visualizes the design process. Novel features also include an automated architecture exploration based on the system models in UML, as well as the automatic back and forward annotation of information in the design flow. The architecture exploration is based on the global optimization of systems that are composed of subsystems, which are then locally optimized for their particular purposes. As a result, the design flow produces an optimized component allocation, task mapping, and scheduling for the described application. In addition, it implements the entire system for FPGA prototyping board. As a case study, the design flow is utilized in the integration of state-of-the-art technology approaches, including a wireless terminal architecture, a network-on-chip, and multiprocessing utilizing RTOS in a SoC. In this study, a central part of a WLAN terminal is modeled, verified, optimized, and prototyped with the presented framework.