Embedded Software Development with eCos
Embedded Software Development with eCos
Hardware/Software Co-Configuration for Multiprocessor SoPC
WSTFES '03 Proceedings of the IEEE Workshop on Software Technologies for Future Embedded Systems
Parallel Direct Solution of Linear Equations on FPGA-Based Machines
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
UML for hardware and software object modeling
UML for real
Symmetric Multiprocessing on Programmable Chips Made Easy
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
UML 2.0 Profile for Embedded System Design
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
UML-based multiprocessor SoC design framework
ACM Transactions on Embedded Computing Systems (TECS)
Implementing a WLAN video terminal using UML and fully automated design flow
EURASIP Journal on Embedded Systems
Evaluating the model accuracy in automated design space exploration
Microprocessors & Microsystems
Automated distribution of UML 2.0 designed applications to a configurable multiprocessor platform
SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
MARTE profile extension for modeling dynamic power management of embedded systems
Journal of Systems Architecture: the EUROMICRO Journal
MCAPI abstraction on FPGA based SoC design
Proceedings of the Annual FPGA Conference
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This paper presents the design and full prototype implementation of a configurable multiprocessor platform that supports distributed execution of applications described in UML 2.0. The platform is comprised of multiple Altera Nios II softcore processors and custom hardware accelerators connected by the Heterogeneous IP Block Interconnection (HIBI) communication architecture. Each processor has a local copy of eCos real-time operating system for the scheduling of multiple application threads. The mapping of a UML application into the proposed platform is presented by distributing a WLAN medium access control protocol onto multiple CPUs. The experiments performed on FPGA show that our approach raises system design to a new level. To our knowledge, this is the first real implementation combining a high-level design flow with a synthesizable platform.