Symmetric Multiprocessing on Programmable Chips Made Easy
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Scalable MPEG-4 encoder on FPGA multiprocessor SOC
EURASIP Journal on Embedded Systems
WSEAS Transactions on Circuits and Systems
Parallel processors architecture in FPGA for the solution of linear equations systems
ICOSSSE '09 Proceedings of the 8th WSEAS international conference on System science and simulation in engineering
FPGA accelerated parallel sparse matrix factorization for circuit simulations
ARC'11 Proceedings of the 7th international conference on Reconfigurable computing: architectures, tools and applications
An FPGA-Based parallel accelerator for matrix multiplications in the newton-raphson method
EUC'05 Proceedings of the 2005 international conference on Embedded and Ubiquitous Computing
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The efficient solution of large systems of linear equations represented by sparse matrices appears in many tasks. LU factorization followed by backward and forward substitutions is widely used for this purpose. Parallel implementations of this computation-intensive process are limited primarily to supercomputers. New generations of Field-Programmable Gate Array (FPGA) technologies enable the implementation of System-On-a-Programmable-Chip (SOPC) computing platforms that provide many opportunities for configurable computing. We present here the design and implementation of a parallel machine for LU factorization on an SOPC board, using multiple instances of a soft processor. A highly parallel Block -Diagonal-Bordered (BDB) algorithm for LU factorization is mapped to our multiprocessor. Our results prove the viability of our FPGA-based approach.