Parallel Direct Solution of Linear Equations on FPGA-Based Machines
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
Area-efficient arithmetic expression evaluation using deeply pipelined floating-point cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architectural modifications to enhance the floating-point performance of FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
WSEAS Transactions on Circuits and Systems
| Hi-index | 0.00 |
This paper presents a parallel array of processors implemented in a Field Programmable Gate Array (FPGA) for the solution of linear equations systems. The solution is performed using the division-free Gaussian elimination method. This algorithm was implemented in integrated processors in a FPGA Spartan 3 of Xilinx. A top-down design was used. The proposed architecture can handle IEEE 754 single and double precision floating-point data and the architecture is implemented in 240 identical processors. Also, an algorithmic complexity of de O(n2) was obtained using a n2 processors scheme that perform the solution of the linear equations. The parallel division-free Gaussian elimination method, the architecturés data distribution, the internal processor-element architecture and the communication scheme between processor elements (PE) are presented. Finally, this paper presents the obtained simulation results and synthesis of the modules designed in Very High Description Language (VHDL) using 40 and 100 Mhz frequencies.