Parallel Direct Solution of Linear Equations on FPGA-Based Machines
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
Area-efficient arithmetic expression evaluation using deeply pipelined floating-point cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architectural modifications to enhance the floating-point performance of FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modular design and implementation of FPGA-based tap-selective maximum-likelihood channel estimator
WSEAS Transactions on Signal Processing
Parallel processors architecture in FPGA for the solution of linear equations systems
ICOSSSE '09 Proceedings of the 8th WSEAS international conference on System science and simulation in engineering
| Hi-index | 0.00 |
This paper presents a parallel architecture for the solution of linear equations systems based on the Division Free Gaussian Elimination Method. This architecture was implemented in a Field Programmable Gate Array (FPGA). The division-free Gaussian elimination method was integrated in identical processors in a FPGA Spartan 3 of Xilinx. A top-down design was used. The proposed architecture can handle IEEE 754 single and double precision floating-point data and the architecture was implemented in 240 processors. Also, an algorithmic complexity of O(n2) was obtained using a n2 processors scheme that perform the solution of the linear equations. Moreover, the parallel division-free Gaussian elimination method, the architecture's data distribution and the internal processor-element (PE) architecture are presented. Finally, this paper presents the obtained simulation results and synthesis of the modules designed in very high-speed integrated circuit hardware description language (VHDL) using 40 and 100 Mhz frequencies.