A Supernodal Approach to Sparse Partial Pivoting
SIAM Journal on Matrix Analysis and Applications
Making sparse Gaussian elimination scalable by static pivoting
SC '98 Proceedings of the 1998 ACM/IEEE conference on Supercomputing
Future Generation Computer Systems - I. High Performance Numerical Methods and Applications. II. Performance Data Mining: Automated Diagnosis, Adaption, and Optimization
An Unsymmetrized Multifrontal LU Factorization
SIAM Journal on Matrix Analysis and Applications
Parallel Direct Solution of Linear Equations on FPGA-Based Machines
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
An overview of SuperLU: Algorithms, implementation, and user interface
ACM Transactions on Mathematical Software (TOMS) - Special issue on the Advanced CompuTational Software (ACTS) Collection
The university of Florida sparse matrix collection
ACM Transactions on Mathematical Software (TOMS)
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Sparse matrix factorization is a critical step for the circuit simulation problem, since it is time consuming and computed repeatedly in the flow of circuit simulation. To accelerate the factorization of sparse matrices, a parallel CPU+FPGA based architecture is proposed in this paper. While the preprocessing of the matrix is implemented on CPU, the parallelism of numeric factorization is explored by processing several columns of the sparse matrix simultaneously on a set of processing elements (PE) in FPGA. To cater for the requirements of circuit simulation, we also modified the Gilbert/Peierls (G/P) algorithm and considered the scalability of our architecture. Experimental results on circuit matrices from the University of Florida Sparse Matrix Collection show that our architecture achieves speedup of 0.5x-5.36x compared with the CPU KLU results.