FPGA accelerated parallel sparse matrix factorization for circuit simulations

Authors:
Wei Wu;Yi Shan;Xiaoming Chen;Yu Wang;Huazhong Yang
Affiliations:
Department of Electronic Engineering, Tsinghua National Laboratory for Information, Tsinghua University, Beijing, China;Department of Electronic Engineering, Tsinghua National Laboratory for Information, Tsinghua University, Beijing, China;Department of Electronic Engineering, Tsinghua National Laboratory for Information, Tsinghua University, Beijing, China;Department of Electronic Engineering, Tsinghua National Laboratory for Information, Tsinghua University, Beijing, China;Department of Electronic Engineering, Tsinghua National Laboratory for Information, Tsinghua University, Beijing, China
Venue:
ARC'11 Proceedings of the 7th international conference on Reconfigurable computing: architectures, tools and applications
Year:
2011

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Abstract

Sparse matrix factorization is a critical step for the circuit simulation problem, since it is time consuming and computed repeatedly in the flow of circuit simulation. To accelerate the factorization of sparse matrices, a parallel CPU+FPGA based architecture is proposed in this paper. While the preprocessing of the matrix is implemented on CPU, the parallelism of numeric factorization is explored by processing several columns of the sparse matrix simultaneously on a set of processing elements (PE) in FPGA. To cater for the requirements of circuit simulation, we also modified the Gilbert/Peierls (G/P) algorithm and considered the scalability of our architecture. Experimental results on circuit matrices from the University of Florida Sparse Matrix Collection show that our architecture achieves speedup of 0.5x-5.36x compared with the CPU KLU results.