Evaluating the model accuracy in automated design space exploration

Authors:
Kalle Holma;Mikko Setälä;Erno Salminen;Marko Hännikäinen;Timo D. Hämäläinen
Affiliations:
Tampere University of Technology, Department of Computer Systems, P.O. Box 553, FI-33101 Tampere, Finland;Sasken Finland Oy, Hermiankatu 12 B, FI-33720 Tampere, Finland;Tampere University of Technology, Department of Computer Systems, P.O. Box 553, FI-33101 Tampere, Finland;Tampere University of Technology, Department of Computer Systems, P.O. Box 553, FI-33101 Tampere, Finland;Tampere University of Technology, Department of Computer Systems, P.O. Box 553, FI-33101 Tampere, Finland
Venue:
Microprocessors & Microsystems
Year:
2008

Citing 11
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Abstract

Design space exploration is used to shorten the design time of system-on-chips (SoCs). Exploration uses abstracted system models that need to be both accurate and fast to simulate. This paper introduces a multi-level communication cost to improve the accuracy of the abstracted models. During the simulation, one of three different communication costs is applied for each inter-task communication event based on the mapping of the communicating tasks. The accuracy of three system abstraction models using the presented communication cost is evaluated with a Motion-JPEG application in a multi-processor SoC with 9 mappings having 1-4 processors. The application is described in Unified Modeling Language (UML) and simulated using transaction generator (TG) simulation engine. According to the results, the average error in frames per second is 4.3% for the modulo model, 5.0% for the trace model, and 12.8% for the probabilistic model compared to FPGA execution. The simulation speed-up is more than 230x compared to low-level cycle-accurate simulation. The results show that with the multi-level communication cost the accuracy is increased significantly without sacrificing the simulation speed.