The SPLASH-2 programs: characterization and methodological considerations
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Parallel Computer Architecture: A Hardware/Software Approach
Parallel Computer Architecture: A Hardware/Software Approach
Traffic Temporal Analysis for Reconfigurable Interconnects in Shared-Memory Systems
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
TrGen: A Traffic Generation System for Interconnection Network Simulators
ICPPW '05 Proceedings of the 2005 International Conference on Parallel Processing Workshops
Predicting reconfigurable interconnect performance in distributed shared-memory systems
Integration, the VLSI Journal
Evaluating the model accuracy in automated design space exploration
Microprocessors & Microsystems
A system-level design methodology for application-specific networks-on-chip
Journal of Embedded Computing - PATMOS 2007 selected papers on low power electronics
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Run-time reconfigurable interconnection networks can provide significant performance gains in shared-memory multiprocessor systems. However, designing such networks is hard, requiring detailed but slow execution-driven simulations, since faster methods are currently not suitable for use with dynamic network topologies. In this paper, we extend one of these methods, synthetic traffic generation, to incorporate the dynamic traffic behavior necessary to accurately determine the performance of a reconfigurable network. Our synthetic traffic flow has the same characteristics as the flow resulting from an execution driven simulation, but can be much shorter: we can gain a reduction in simulation time of up to 100x at only a limited expense in accuracy. This way, it is possible to quickly analyze the dynamic interconnect requirements of an application and evaluate various aspects of a proposed reconfigurable interconnect implementation.