Predicting reconfigurable interconnect performance in distributed shared-memory systems

Authors:
W. Heirman;J. Dambre;I. Artundo;C. Debaes;H. Thienpont;D. Stroobandt;J. Van Campenhout
Affiliations:
ELIS Department, Ghent University, Sint-Pietersnieuwstraat 41, 9000 Ghent, Belgium;ELIS Department, Ghent University, Sint-Pietersnieuwstraat 41, 9000 Ghent, Belgium;TONA Department, Free University of Brussels, Pleinlaan 2, 1050 Brussels, Belgium;TONA Department, Free University of Brussels, Pleinlaan 2, 1050 Brussels, Belgium;TONA Department, Free University of Brussels, Pleinlaan 2, 1050 Brussels, Belgium;ELIS Department, Ghent University, Sint-Pietersnieuwstraat 41, 9000 Ghent, Belgium;ELIS Department, Ghent University, Sint-Pietersnieuwstraat 41, 9000 Ghent, Belgium
Venue:
Integration, the VLSI Journal
Year:
2007

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Abstract

Reconfigurable interconnection networks have been shown to benefit performance in distributed shared-memory multiprocessor machines. Usually, performance measurements for these networks require large numbers of slow full-system simulations, making design-space exploration a cumbersome and time-consuming task. In this paper, we present a prediction model for the performance of a reconfigurable network, based on a single full-system simulation and a much shorter, per parameter set post-processing phase. We provide simulation results establishing the relative accuracy of the technique and analyze the impact of several assumptions that were made. With our method, a quick evaluation of a large range of parameters is now possible, allowing the designer to make well-founded design trade-offs.