Prototyping of embedded digital systems from SDL language: a case study

  • Authors:

  • C. A. M. Marcon;F. Hessel;A. M. Amory;L. H. L. Ries;F. G. Moraes;N. L. V. Calazans

  • Affiliations:

  • California Univ., Riverside, CA, USA;California Univ., Riverside, CA, USA;California Univ., Riverside, CA, USA;Eindhoven Univ. of Technol., Netherlands;Eindhoven Univ. of Technol., Netherlands;-

  • Venue:
  • HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
  • Year:
  • 2002

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Abstract

The goal of this paper is to evaluate the performance of embedded digital systems generated from a system level description language. The target language is SDL, which is automatically synthesized with a codesign tool, resulting in VHDL and C descriptions. The codesign tool is responsible for software, hardware and communication synthesis. Two case studies are presented, exploring area and delay results. The results concern only the hardware synthesis, since the goal is to compare the performance of systems generated from hand coded HDL descriptions against a synthesized HDL. The analysis of the advantages and drawbacks of this automatic hardware design flow and the evaluation of the commercial tools integration are also reported.