The Chinook hardware/software co-synthesis system
ISSS '95 Proceedings of the 8th international symposium on System synthesis
GTX: the MARCO GSRC technology extrapolation system
Proceedings of the 37th Annual Design Automation Conference
Performance assessment of embedded Hw/Sw systems
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Exploring Microprocessor Architectures for Gigascale Integration
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
Facilitating Interconnect-Based VLSI Design
MSE '97 Proceedings of the 1997 International Conference on Microelectronics Systems Education (MSE '97)
A Systematic Approach to Exploring Embedded System Architectures at Multiple Abstraction Levels
IEEE Transactions on Computers
UML-based multiprocessor SoC design framework
ACM Transactions on Embedded Computing Systems (TECS)
A framework introducing model reversibility in SoC design space exploration
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
Hi-index | 0.00 |
In this paper we present a flexible performance estimation tool called Nessie developed to provide system-on-chip designers with automated multi-objective design space exploration and its related tool called Yeti building and executing reusable closed-formed models. After reviewing the existing closed-formed expressions based and application/platform mapping performance estimation tools, we propose an hybrid tool to cope with their limitations. We present a brief summary of the functionalities of Yeti and describe Nessie, our hierarchical application/platform performance estimation mapping tool which banalizes all the degrees of freedom for in-depth design space exploration and introduces multi-objective modeling. Through this paper, we explain how the combination of these tools provides the designer with innovative and powerful functionalities for performance prediction at the earlier stages of the design flow.