Uninterpreted Co-Simulation for Performance Evaluation of Hw/Sw Systems
CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
A Generic RTOS Model for Real-time Systems Simulation with SystemC
Proceedings of the conference on Design, automation and test in Europe - Volume 3
A Multi-objective and Hierarchical Exploration Tool for SoC Performance Estimation
SAMOS '08 Proceedings of the 8th international workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
Performance Analysis Framework for High-Level Language Applications in Reconfigurable Computing
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Instrumentation-based tool for latency measurements
Proceedings of the 2nd ACM/SPEC International Conference on Performance engineering
Communication visualization for bottleneck detection of high-level synthesis applications
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
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Performance assessment of embedded Hw/Sw systems built with various types of VLSI components, i.e. heterogeneous multi-processor architectures, is important to help the development of complex real-time applications. To design such a tool, two issues are to be solved, relevant information gathered simultaneously on several components without disturbing the application behavior, and the display of the performance results in a way which is easily interpreted by designers. This paper presents an interesting solution for the two above issues. We first describe what the goal for designers is and what kind of applications are concerned. Then we describe the principle of collecting an event trace and the technique to evaluate the selected performance indexes. The monitoring technique, based on a specific ASIC, is nonintrusive and allows to capture real-time event occurrences from software tasks and even from hardware functions implemented in ASICs. Each event is automatically time-stamped, collected and processed in real-time to evaluate the performance indexes selected by the designer. We also describe the display tool which clearly shows to the designer the results according to different representations. This technique and the associated real-time performance analyzer are integrated in a whole development process based on the MCSE methodology.