HPCVIEW: A Tool for Top-down Analysis of Node Performance
The Journal of Supercomputing
Performance assessment of embedded Hw/Sw systems
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Source Level Debugger for the Sea Cucumber Synthesizing Compiler
FCCM '03 Proceedings of the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Application Development on the SRC Computers, Inc. Systems
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Papers - Volume 01
Instrumenting Bitstreams for Debugging FPGA Circuits
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Owl: next generation system monitoring
Proceedings of the 2nd conference on Computing frontiers
Toward Scalable Performance Visualization with Jumpshot
International Journal of High Performance Computing Applications
Performance characterization of molecular dynamics techniques for biomolecular simulations
Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programming
The Tau Parallel Performance System
International Journal of High Performance Computing Applications
Formulating and implementing profiling over adaptive ranges
ACM Transactions on Architecture and Code Optimization (TACO)
Practical fpga programming in c
Practical fpga programming in c
Performance Analysis with High-Level Languages for High-Performance Reconfigurable Computing
FCCM '08 Proceedings of the 2008 16th International Symposium on Field-Programmable Custom Computing Machines
Platform-aware bottleneck detection for reconfigurable computing applications
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Communication visualization for bottleneck detection of high-level synthesis applications
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Microprocessors & Microsystems
Performance analysis techniques for multi-soft-core and many-soft-core systems
International Journal of Reconfigurable Computing
Journal of Real-Time Image Processing
Performance modeling for FPGAs: extending the roofline model with high-level synthesis tools
International Journal of Reconfigurable Computing
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High-Level Languages (HLLs) for Field-Programmable Gate Arrays (FPGAs) facilitate the use of reconfigurable computing resources for application developers by using familiar, higher-level syntax, semantics, and abstractions, typically enabling faster development times than with traditional Hardware Description Languages (HDLs). However, programming at a higher level of abstraction is typically accompanied by some loss of performance as well as reduced transparency of application behavior, making it difficult to understand and improve application performance. While runtime tools for performance analysis are often featured in development with traditional HLLs for sequential and parallel programming, HLL-based development for FPGAs has an equal or greater need yet lacks these tools. This article presents a novel and portable framework for runtime performance analysis of HLL applications for FPGAs, including an automated tool for performance analysis of designs created with Impulse C, a commercial HLL for FPGAs. As a case study, this tool is used to successfully locate performance bottlenecks in a molecular dynamics kernel in order to gain speedup.