Platform-aware bottleneck detection for reconfigurable computing applications

  • Authors:

  • Seth Koehler;Greg Stitt;Alan D. George

  • Affiliations:

  • NSF Center for High Performance Reconfigurable Computing, University of Florida, Gainesville, FL;NSF Center for High Performance Reconfigurable Computing, University of Florida, Gainesville, FL;NSF Center for High Performance Reconfigurable Computing, University of Florida, Gainesville, FL

  • Venue:
  • ACM Transactions on Reconfigurable Technology and Systems (TRETS)
  • Year:
  • 2011

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Abstract

Reconfigurable Computing (RC) has the potential to provide substantial performance benefits and yet simultaneously consume less power than traditional microprocessors or GPUs. While experimental performance analysis of RC applications has previously been shown crucial for achieving this potential, existing methods still require application designers to manually locate bottlenecks and determine appropriate optimizations, typically requiring significant designer expertise and effort. Worse, the diversity of platforms employed by RC applications further complicates the process of detecting bottlenecks and formulating optimizations. To address these shortcomings, we first discuss our platform-template system, which enables a performance analysis tool to perform more accurate bottleneck detection and achieve a higher degree of portability across diverse FPGA systems. We then provide details for our implementation of these concepts and techniques in the Reconfigurable Computing Application Performance (ReCAP) tool. Next, we present a taxonomy of common RC bottlenecks, providing associated detection and optimization strategies for each bottleneck, which we use to populate ReCAP's knowledge base for bottleneck detection. Finally, we demonstrate the utility of our approach via two application case studies across a total of three platforms.