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JouleSort: a balanced energy-efficiency benchmark
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Computation Cost in Grid Computing Environments
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Proceedings of the VLDB Endowment
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Proceedings of the 36th annual international symposium on Computer architecture
Energy Smart Management of Scientific Data
SSDBM 2009 Proceedings of the 21st International Conference on Scientific and Statistical Database Management
Tracking the power in an enterprise decision support system
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ACM SIGOPS Operating Systems Review
Future scaling of processor-memory interfaces
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CCNC'10 Proceedings of the 7th IEEE conference on Consumer communications and networking conference
A consumer-device-supported IPTV network
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NapSAC: design and implementation of a power-proportional web cluster
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Towards energy proportional cloud for data processing frameworks
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FOSD '10 Proceedings of the 2nd International Workshop on Feature-Oriented Software Development
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QMD: exploiting flash for energy efficient disk arrays
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WOOT'11 Proceedings of the 5th USENIX conference on Offensive technologies
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In the late 1990s, our research group at DEC was one of a growing number of teams advocating the CMP (chip multiprocessor) as an alternative to highly complex single-threaded CPUs. We were designing the Piranha system,1 which was a radical point in the CMP design space in that we used very simple cores (similar to the early RISC designs of the late ’80s) to provide a higher level of thread-level parallelism. Our main goal was to achieve the best commercial workload performance for a given silicon budget.