Performance and power of cache-based reconfigurable computing

  • Authors:

  • Andrew Putnam;Susan Eggers;Dave Bennett;Eric Dellinger;Jeff Mason;Henry Styles;Prasanna Sundararajan;Ralph Wittig

  • Affiliations:

  • University of Washington, Seattle, WA, USA;University of Washington, Seattle, WA, USA;Xilinx, Inc., San Jose, CA, CA, USA;Xilinx, Inc., San Jose, CA, CA, USA;Xilinx, Inc., San Jose, CA, CA, USA;Xilinx, Inc., San Jose, CA, CA, USA;Xilinx, Inc., San Jose, CA, CA, USA;Xilinx, Inc., San Jose, CA, CA, USA

  • Venue:
  • Proceedings of the 36th annual international symposium on Computer architecture
  • Year:
  • 2009

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Abstract

Many-cache is a memory architecture that efficiently supports caching in commercially available FPGAs. It facilitates FPGA programming for high-performance computing (HPC) developers by providing them with memory performance that is greater and power consumption that is less than their current CPU platforms, but without sacrificing their familiar, C-based programming environment. Many-cache creates multiple, multi-banked caches on top of an FGPA's small, independent memories, each targeting a particular data structure or region of memory in an application and each customized for the memory operations that access it. The caches are automatically generated from C source by the CHiMPS C-to-FPGA compiler. This paper presents the analyses and optimizations of the CHiMPS compiler that construct many-cache caches. An architectural evaluation of CHiMPS-generated FPGAs demonstrates a performance advantage of 7.8x (geometric mean) over CPU-only execution of the same source code, FPGA power usage that is on average 4.1x less, and consequently performance per watt that is also greater, by a geometric mean of 21.3x.