Computer arithmetic: algorithms and hardware designs
Computer arithmetic: algorithms and hardware designs
Reactive Computer Vision System with Reconfigurable Architecture
ICVS '99 Proceedings of the First International Conference on Computer Vision Systems
Sassy: A Language and Optimizing Compiler for Image Processing on Reconfigurable Computing Systems
ICVS '99 Proceedings of the First International Conference on Computer Vision Systems
Real-Time 2-D Feature Detection on a Reconfigurable Computer
CVPR '98 Proceedings of the IEEE Computer Society Conference on Computer Vision and Pattern Recognition
Real-time stereo vision on the PARTS reconfigurable computer
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Mapping of generalized template matching onto reconfigurable computers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Compile-time area estimation for LUT-based FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A stochastic bitwidth estimation technique for compact and low-power custom processors
ACM Transactions on Embedded Computing Systems (TECS)
Performance and power of cache-based reconfigurable computing
Proceedings of the 36th annual international symposium on Computer architecture
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
Portable, flexible, and scalable soft vector processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.03 |
At the first ICVS, we presented SA-C ("sassy"), a single-assignment variant of the C programming language designed to exploit both coarse-grain and fine-grain parallelism in computer vision and image processing applications. This paper presents a new optimizing compiler that maps SA-C source code onto field programmable gate array (FPGA) configurations. The compiler allows programmers to exploit FPGAs as inexpensive and massively parallel processors by writing high-level source code rather than hardware-level circuit designs. We present several examples of simple image-based programs and the optimizations that are automatically applied to them during compilation, and compare their performance on FPGAs and Pentiums of similar ages. From this, we determine what types of applications benefit from current FPGA technology, and conclude with some speculations on the future development of FPGAs and their expanding role in computer vision systems.