Fast compilation for pipelined reconfigurable fabrics
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A C compiler for a processor with a reconfigurable functional unit
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Co-Synthesis to a Hybrid RISC/FPGA Architecture
Journal of VLSI Signal Processing Systems - Special issue on VLSI on custom computing technology
Journal of VLSI Signal Processing Systems - Special issue on VLSI on custom computing technology
Matching and searching analysis for parallel hardware implementation on FPGAs
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
A decade of reconfigurable computing: a visionary retrospective
Proceedings of the conference on Design, automation and test in Europe
Coarse grain reconfigurable architecture (embedded tutorial)
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
A framework for reconfigurable computing: task scheduling and context management
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
Compilation for Adaptive Computing Systems Using Complex Parameterized Hardware Objects
The Journal of Supercomputing
Parallel dedicated hardware devices for heterogeneous computations
Proceedings of the 2001 ACM/IEEE conference on Supercomputing
Dependable Computing and Online Testing in Adaptive and Configurable Systems
IEEE Design & Test
Reconfigurable Instruction Set Processors from a Hardware/Software Perspective
IEEE Transactions on Software Engineering
A Compiler Directed Approach to Hiding Configuration Latency in Chameleon Processors
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
StReAm: Object-Oriented Programming of Stream Architectures Using PAM-Blox
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Compilation Increasing the Scheduling Scope for Multi-memory-FPGA-Based Custom Computing Machines
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Task-Parallel Programming of Reconfigurable Systems
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
XPP-VC: A C Compiler with Temporal Partitioning for the PACT-XPP Architecture
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Memory Access Schemes for Configurable Processors
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
High Level Synthesis for Programmable Devices: The HADES Project
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
Hardware/software partitioning of software binaries
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Codesign-extended applications
Proceedings of the tenth international symposium on Hardware/software codesign
Global resource sharing for synthesis of control data flow graphs on FPGAs
Proceedings of the 40th annual Design Automation Conference
Compiler-generated communication for pipelined FPGA applications
Proceedings of the 40th annual Design Automation Conference
Enabling Automatic Module Generation for FCCM Compilers
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Pipeline Vectorization for Reconfigurable Systems
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Parallelizing Applications into Silicon
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Automatic Allocation of Arrays to Memories in FPGA Processors with Multiple Memory Banks
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Automatic Synthesis of Data Storage and Control Structures for FPGA-Based Computing Engines
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
An ACS Robotic Control Algorithm with Fault Tolerant Capabilities
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Stream-Oriented FPGA Computing in the Streams-C High Level Language
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
A MATLAB Compiler for Distributed, Heterogeneous, Reconfigurable Computing Systems
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Mapping of generalized template matching onto reconfigurable computers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
ACM Transactions on Embedded Computing Systems (TECS)
Custom Data Layout for Memory Parallelism
Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
CODACS Prototype: CHIARA Language and Its Compilers
ICDCSW '04 Proceedings of the 24th International Conference on Distributed Computing Systems Workshops - W7: EC (ICDCSW'04) - Volume 7
The MOLEN Polymorphic Processor
IEEE Transactions on Computers
Automatic generation of application-specific systems based on a micro-programmed Java core
Proceedings of the 2005 ACM symposium on Applied computing
Cost Sensitive Modulo Scheduling in a Loop Accelerator Synthesis System
Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture
Interprocedural Compiler Optimization for Partial Run-Time Reconfiguration
Journal of VLSI Signal Processing Systems
Proceedings of the 41st annual Design Automation Conference
Increasing hardware efficiency with multifunction loop accelerators
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
The Molen compiler for reconfigurable processors
ACM Transactions on Embedded Computing Systems (TECS)
A wire delay-tolerant reconfigurable unit for a clustered programmable-reconfigurable processor
Microprocessors & Microsystems
A code refinement methodology for performance-improved synthesis from C
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Synthesis of reconfigurable high-performance multicore systems
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
IEICE - Transactions on Information and Systems
Performance and power of cache-based reconfigurable computing
Proceedings of the 36th annual international symposium on Computer architecture
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
Compiling for reconfigurable computing: A survey
ACM Computing Surveys (CSUR)
Bridging the gap between compilation and synthesis in the DEFACTO system
LCPC'01 Proceedings of the 14th international conference on Languages and compilers for parallel computing
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Implementation of a programming environment with a multithread model for reconfigurable systems
ACM SIGARCH Computer Architecture News
Interprocedural optimization for dynamic hardware configurations
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Exploring many-core design templates for FPGAs and ASICs
International Journal of Reconfigurable Computing - Special issue on Selected Papers from the International Conference on Reconfigurable Computing and FPGAs (ReConFig'10)
C2FPGA-A dependency-timing graph design methodology
Journal of Parallel and Distributed Computing
| Hi-index | 0.00 |
Hybrid architectures combining conventional processors with configurable logic resources enable efficient coordination of control with datapath computation. With integration of the two components on a single device, loop control and data-dependent branching can be handled by the conventional processor, while regular datapath computation occurs on the configurable hardware. This paper describes a novel pragma-based approach to programming such hybrid devices. The NAPA C language provides pragma directives so that the programmer (or an automatic partitioner) can specify where data is to reside and where computation is to occur with statement-level granularity. The NAPA C compiler, targeting National Semiconductor's NAPA1000 chip, performs semantic analysis of the pragma-annotated program and co-synthesizes a conventional program executable combined with a configuration bit stream for the adaptive logic. Compiler optimizations include synthesis of hardware pipelines from pipelineable loops.