Advanced loop optimizations for parallel computers
Proceedings of the 1st International Conference on Supercomputing
Supercompilers for parallel and vector computers
Supercompilers for parallel and vector computers
Exploiting parallelism on a fine-grained MIMD architecture based upon channel queues
International Journal of Parallel Programming
The definition of dependence distance
ACM Transactions on Programming Languages and Systems (TOPLAS)
A datapath synthesis system for the reconfigurable datapath architecture
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
LAPACK Users' guide (third ed.)
LAPACK Users' guide (third ed.)
System Design with SystemC
Proceedings of the 15th international symposium on System Synthesis
Scheduling Data-Flow Graphs via Retiming and Unfolding
IEEE Transactions on Parallel and Distributed Systems
Generating Parallel Programs from the Wavefront Design Pattern
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
DEFACTO: A Design Environment for Adaptive Computing Technology
Proceedings of the 11 IPPS/SPDP'99 Workshops Held in Conjunction with the 13th International Parallel Processing Symposium and 10th Symposium on Parallel and Distributed Processing
Accelerating Matrix Product on Reconfigurable Hardware for Signal Processing
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Implementing C Algorithms in Reconfigurable Hardware Using C2Verilog
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
NAPA C: Compiling for a Hybrid RISC/FPGA Architecture
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
The Transmogrifier C hardware description language and compiler for FPGAs
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
C++ Expression Templates Performance Issues in Scientific Computing
IPPS '98 Proceedings of the 12th. International Parallel Processing Symposium on International Parallel Processing Symposium
International Journal of High Performance Computing Applications
The Tau Parallel Performance System
International Journal of High Performance Computing Applications
Examining the viability of FPGA supercomputing
EURASIP Journal on Embedded Systems
Implementation of the Smith-Waterman algorithm on a reconfigurable supercomputing platform
HPRCTA '07 Proceedings of the 1st international workshop on High-performance reconfigurable computing technology and applications: held in conjunction with SC07
Cell-SWat: modeling and scheduling wavefront computations on the cell broadband engine
Proceedings of the 5th conference on Computing frontiers
A matrix product accelerator for field programmable systems on chip
Microprocessors & Microsystems
High-Performance Designs for Linear Algebra Operations on Reconfigurable Hardware
IEEE Transactions on Computers
Practical fpga programming in c
Practical fpga programming in c
Interactive Visualization and Analysis of Transitional Flow
IEEE Transactions on Visualization and Computer Graphics
Computer Organization and Design: The Hardware/Software Interface
Computer Organization and Design: The Hardware/Software Interface
Optimal Loop Unrolling and Shifting for Reconfigurable Architectures
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
C-based design methodology for FPGA implementation of clustalW MSA
PRIB'07 Proceedings of the 2nd IAPR international conference on Pattern recognition in bioinformatics
Designing Modular Hardware Accelerators in C with ROCCC 2.0
FCCM '10 Proceedings of the 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines
Proceedings of the 19th ACM International Symposium on High Performance Distributed Computing
| Hi-index | 0.00 |
In this paper, we present a design methodology that uses a combined graphical and scheduling technique to map C-based high level language (HLL) based applications to FPGA. Although there are a number of approaches addressing the mapping from HLL to hardware, many of these existing solutions either require a steep learning curve or do not produce an appropriate mapping pattern for the hardware platform. We provide a solution to this problem, by analyzing the data flow and data dependencies in the given code and proposing a scheduling patterns for the given algorithm. We then provide a suitable mapping pattern for the hardware platform. We use the mapping pattern to deliver synthesizable HDL (Verilog) code. We demonstrate our design methodology with results from different real-time case studies that are based on different algorithms.