FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Reconfigurable Multiplier for Virtex FPGA Family
FPL '99 Proceedings of the 9th International Workshop on Field-Programmable Logic and Applications
A Re-evaluation of the Practicality of Floating-Point Operations on FPGAs
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
PAM-Blox: High Performance FPGA Design for Adaptive Computing
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Custom Coprocessor Based Matrix Algorithms for Image and Signal Processing
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Energy-Efficient Matrix Multiplication on FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
C2FPGA-A dependency-timing graph design methodology
Journal of Parallel and Distributed Computing
| Hi-index | 0.00 |
This paper investigates how some of the new features of the Xilinx Virtex FPGA may be used to support efficient and optimised implementation of matrix product based on Multiply and Accumulate (MAC) such operations are frequently used in signal applications. The principle new features that have been investigated are the Block RAM and the fully digital Delay-Locked Loop (DLL). The approach used for the matrix multiplication algorithm employs the idea used in the modified Booth encoder multiplication using Wallace Trees addition. Preliminary performance results and comparisons with similar algorithms implemented on multi-FPGA platforms have shown better performance for the proposed architecture.