Interprocedural optimization for dynamic hardware configurations

Authors:
Elena Moscu Panainte;Koen Bertels;Stamatis Vassiliadis
Affiliations:
Computer Engineering Lab, Delft University of Technology, The Netherlands;Computer Engineering Lab, Delft University of Technology, The Netherlands;Computer Engineering Lab, Delft University of Technology, The Netherlands
Venue:
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Year:
2005

Citing 7
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Abstract

Little research in compiler optimizations has been undertaken to eliminate or diminish the negative influence on performance of the huge reconfiguration latency of the available FPGA platforms. In this paper, we propose an interprocedural optimization that minimizes the number of executed hardware configuration instructions taking into account constraints such as the ”FPGA-area placement conflicts” between the available hardware configurations. The proposed algorithm allows the anticipation of hardware configuration instructions up to the application's main procedure. The presented results show that our optimization produces a reduction of up to 3 – 5 order of magnitude of the number of executed hardware configuration instructions.