A Reconfigurable Processor Architecture and Software Development Environment for Embedded Systems

Authors:
F. Campi;A. Cappelli;R. Guerrieri;A. Lodi;M. Toma;A. La Rosa;L. Lavagno;C. Passerone;R. Canegallo
Affiliations:
-;-;-;-;-;-;-;-;-
Venue:
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
Year:
2003

Citing 0
Cited 3

Interprocedural Compiler Optimization for Partial Run-Time Reconfiguration

Journal of VLSI Signal Processing Systems
The Molen compiler for reconfigurable processors

ACM Transactions on Embedded Computing Systems (TECS)
Interprocedural optimization for dynamic hardware configurations

SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation

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Abstract

Flexibility, high computing power and low energy consumption are strong guidelines when designing new generation embedded processors. Traditional architectures are no longer suitable to provide a good compromise among these contradictory implementation requirements. In this paper we present a new reconfigurable processor that tightly couples a VLIW architecture with a configurable unit implementing an additional configurable pipeline. A software development environment is also introduced providing a user-friendly tool for application development and performance simulation. Finally, we show that the HW/SW reconfigurable platform proposed achieves dramatic improvement in both speed and energy consumption on signal processing computation kernels.