A C compiler for a processor with a reconfigurable functional unit
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Compaan: deriving process networks from Matlab for embedded signal processing architectures
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Design and Implementation of the MorphoSys Reconfigurable ComputingProcessor
Journal of VLSI Signal Processing Systems - Special issue on VLSI on custom computing technology
DEFACTO: A Design Environment for Adaptive Computing Technology
Proceedings of the 11 IPPS/SPDP'99 Workshops Held in Conjunction with the 13th International Parallel Processing Symposium and 10th Symposium on Parallel and Distributed Processing
Field-Programmable Custom Computing Machines - A Taxonomy -
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Optimal and efficient speculation-based partial redundancy elimination
Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
NAPA C: Compiling for a Hybrid RISC/FPGA Architecture
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
ConCISe: A Compiler-Driven CPLD-Based Instruction Set Accelerator
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A Reconfigurable Processor Architecture and Software Development Environment for Embedded Systems
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
System Design Using Kahn Process Networks: The Compaan/Laura Approach
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Strategies for dynamic memory allocation in hybrid architectures
Proceedings of the 6th ACM conference on Computing frontiers
Efficient memory management for hardware accelerated Java Virtual Machines
ACM Transactions on Design Automation of Electronic Systems (TODAES)
MinDeg: a performance-guided replacement policy for run-time reconfigurable accelerators
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
International Journal of Reconfigurable Computing - Selected papers from ReCoSoc08
Mapping of a film grain removal algorithm to a heterogeneous reconfigurable architecture
Proceedings of the Conference on Design, Automation and Test in Europe
Runtime multitasking support on polymorphic platforms
ACM SIGARCH Computer Architecture News
Design, implementation, and verification of an adaptable processor in lava HDL
ARC'11 Proceedings of the 7th international conference on Reconfigurable computing: architectures, tools and applications
Journal of Signal Processing Systems
QUAD: a memory access pattern analyser
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
ESL Design and Verification: A Prescription for Electronic System Level Methodology
ESL Design and Verification: A Prescription for Electronic System Level Methodology
Communication-aware HW/SW co-design for heterogeneous multicore platforms
Proceedings of the 2012 Workshop on Dynamic Analysis
Processor design using a functional hardware description language
Microprocessors & Microsystems
ACM Transactions on Embedded Computing Systems (TECS)
| Hi-index | 0.00 |
In this paper, we describe the compiler developed to target the Molen reconfigurable processor and programming paradigm. The compiler automatically generates optimized binary code for C applications, based on pragma annotation of the code executed on the reconfigurable hardware. For the IBM PowerPC 405 processor included in the Virtex II Pro platform FPGA, we implemented code generation, register, and stack frame allocation following the PowerPC EABI (embedded application binary interface). The PowerPC backend has been extended to generate the appropriate instructions for the reconfigurable hardware and data transfer, taking into account the information of the specific hardware implementations and system. Starting with an annotated C application, a complete design flow has been integrated to generate the executable bitstream for the reconfigurable processor. The flexible design of the proposed infrastructure allows to consider the special features of the reconfigurable architectures. In order to hide the reconfiguration latencies, we implemented an instruction-scheduling algorithm for the dynamic hardware configuration instructions. The algorithm schedules, in advance, the hardware configuration instructions, taking into account the conflicts for the reconfigurable hardware resources (FPGA area) between the hardware operations. To verify the Molen compiler, we used the multimedia video frame M-JPEG encoder of which the extended discrete cosine transform (DCT*) function was mapped on the FPGA. We obtained an overall speedup of 2.5 (about 84% efficiency over the maximal theoretical speedup of 2.96). The performance efficiency is achieved using automatically generated nonoptimized DCT* hardware implementation. The instruction-scheduling algorithm has been tested for DCT, quantization, and VLC operations. Based on simulation results, we determine that, while a simple scheduling produces a significant performance decrease, our proposed scheduling contributes for up to 16x M-JPEG encoder speedup.