A C compiler for a processor with a reconfigurable functional unit

Authors:
Zhi Alex Ye;Nagaraj Shenoy;Prithviraj Baneijee
Affiliations:
Department of Electrical and Computer Engineering, Northwestern University, Evanston, IL;Department of Electrical and Computer Engineering, Northwestern University, Evanston, IL;Department of Electrical and Computer Engineering, Northwestern University, Evanston, IL
Venue:
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Year:
2000

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Abstract

This paper describes a C compiler for a mixed Processor/FPGA architecture where the FPGA is a Reconfigurable Functional Unit (RFU). It presents three compilation techniques that can extract computations from applications to put into the RFU. The results show that large instruction sequences can be created and extracted by these techniques. An average speedup of 2.6 is achieved over a set of benchmarks.