A partitioning flow for accelerating applications in processor-FPGA systems

Authors:
Michalis D. Galanis;Gregory Dimitroulakos;Costas E. Goutis
Affiliations:
VLSI Design Laboratory, Electrical & Computer Engineering Department, University of Patras, Greece;VLSI Design Laboratory, Electrical & Computer Engineering Department, University of Patras, Greece;VLSI Design Laboratory, Electrical & Computer Engineering Department, University of Patras, Greece
Venue:
ICCOMP'05 Proceedings of the 9th WSEAS International Conference on Computers
Year:
2005

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Abstract

This paper presents a hardware/software partitioning flow for improving performance in systems-on- chip comprised by processor and Field Programmable Gate Array. Speedups are achieved by executing critical software parts on the reconfigurable FPGA logic. A generic hybrid system architecture is considered by the methodology. The partitioning flow uses an automated analysis process at the basic-block level for detecting critical application parts. Two different instances of the generic platform and five real-world applications are used in the experiments. The analytical experimentation illustrates that the speedup of the applications ranges from 1.3 to 3.7 relative to an all software solution.