A low power hardware/software partitioning approach for core-based embedded systems

System-level power optimization: techniques and tools

ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design

System-level power optimization: techniques and tools

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Efficient power co-estimation techniques for system-on-chip design

DATE '00 Proceedings of the conference on Design, automation and test in Europe

Integrated hardware-software co-synthesis for design of embedded systems under power and latency constraints

Proceedings of the conference on Design, automation and test in Europe

A system-level energy minimization approach using datapath width optimization

ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design

Partitioning sequential programs for CAD using a three-step approach

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Low power system scheduling and synthesis

Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design

Cosimulation-based power estimation for system-on-chip design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Energy Advantages of Microprocessor Platforms with On-Chip Configurable Logic

IEEE Design & Test

Low Power Distributed Embedded Systems: Dynamic Voltage Scaling and Synthesis

HiPC '02 Proceedings of the 9th International Conference on High Performance Computing

Early Power Estimation for System-on-Chip Designs

PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation

Low Power Synthesis Methodology with Data Format Optimization Applied on a DWT

Journal of VLSI Signal Processing Systems

Hardware/software partitioning of software binaries

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design

Codesign-extended applications

Proceedings of the tenth international symposium on Hardware/software codesign

Dynamic hardware/software partitioning: a first approach

Proceedings of the 40th annual Design Automation Conference

Quality of EDA CAD Tools: Definitions, Metrics and Directions

ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design

A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning

Proceedings of the conference on Design, automation and test in Europe - Volume 1

Energy savings and speedups from partitioning critical software loops to hardware in embedded systems

ACM Transactions on Embedded Computing Systems (TECS)

A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning

Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

A Decompilation Approach to Partitioning Software for Microprocessor/FPGA Platforms

Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

Dynamic reconfiguration with binary translation: breaking the ILP barrier with software compatibility

Proceedings of the 42nd annual Design Automation Conference

Hardware/software partitioning of software binaries: a case study of H.264 decode

CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

Profiling soft-core processor applications for hardware/software partitioning

Journal of Systems Architecture: the EUROMICRO Journal

Layout conscious approach and bus architecture synthesis for hardware/software codesign of systems on chip optimized for speed

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Performance improvements from partitioning applications to FPGA hardware in embedded SoCs

The Journal of Supercomputing

Partitioning Methodology for Heterogeneous Reconfigurable Functional Units

The Journal of Supercomputing

Automated framework for partitioning DSP applications in hybrid reconfigurable platforms

Microprocessors & Microsystems

Genetic algorithms for hardware-software partitioning and optimal resource allocation

Journal of Systems Architecture: the EUROMICRO Journal

Low-power warp processor for power efficient high-performance embedded systems

Proceedings of the conference on Design, automation and test in Europe

Two-level microprocessor-accelerator partitioning

Proceedings of the conference on Design, automation and test in Europe

C is for circuits: capturing FPGA circuits as sequential code for portability

Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays

Hardware/software partitioning with multi-version implementation exploration

Proceedings of the 18th ACM Great Lakes symposium on VLSI

A partitioning flow for accelerating applications in processor-FPGA systems

ICCOMP'05 Proceedings of the 9th WSEAS International Conference on Computers

Enhancing energy efficiency of processor-based embedded systems through post-fabrication ISA extension

Proceedings of the 13th international symposium on Low power electronics and design

Hardware/software partitioning of floating point software applications to fixed-pointed coprocessor circuits

CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis

Algorithmic aspects for power-efficient hardware/software partitioning

Mathematics and Computers in Simulation

Dynamic and On-Line Design Space Exploration for Reconfigurable Architectures

Transactions on High-Performance Embedded Architectures and Compilers I

Design and implementation of a MicroBlaze-based warp processor

ACM Transactions on Embedded Computing Systems (TECS)

Scalability and parallel execution of warp processing: dynamic hardware/software partitioning

International Journal of Parallel Programming

Autonomous hardware/software partitioning and voltage/frequency scaling for low-power embedded systems

ACM Transactions on Design Automation of Electronic Systems (TODAES)

A systematic approach to profiling for hardware/software partitioning

Computers and Electrical Engineering

Design flow for optimizing performance in processor systems with on-chip coarse-grain reconfigurable logic

IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing

Efficient hardware-based nonintrusive dynamic application profiling

ACM Transactions on Embedded Computing Systems (TECS)

Neurocomputing for minimizing energy consumption of real-time operating system in the system-on-a-chip

ICONIP'06 Proceedings of the 13th international conference on Neural information processing - Volume Part III

Low power hardware-software partitioning algorithm for heterogeneous distributed embedded systems

EUC'06 Proceedings of the 2006 international conference on Embedded and Ubiquitous Computing

Performance gains from partitioning embedded applications in Processor-FPGA socs

PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation

Architecture customization of on-chip reconfigurable accelerators

ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies

An overseer control methodology for data adaptable embedded systems

Proceedings of the 6th International Workshop on Multi-Paradigm Modeling