High-level power modeling, estimation, and optimization
DAC '97 Proceedings of the 34th annual Design Automation Conference
System-level synthesis of low-power hard real-time systems
DAC '97 Proceedings of the 34th annual Design Automation Conference
COSYN: hardware-software co-synthesis of embedded systems
DAC '97 Proceedings of the 34th annual Design Automation Conference
Hardware-software co-design of embedded systems: the POLIS approach
Hardware-software co-design of embedded systems: the POLIS approach
A framework for estimation and minimizing energy dissipation of embedded HW/SW systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
A low power hardware/software partitioning approach for core-based embedded systems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Synchronous equivalence for embedded systems: a tool for design exploration
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Efficient power co-estimation techniques for system-on-chip design
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Dynamic Power Management: Design Techniques and CAD Tools
Dynamic Power Management: Design Techniques and CAD Tools
Low Power Digital CMOS Design
A computer-aided design methodology for low power sequential logic circuits
A computer-aided design methodology for low power sequential logic circuits
| Hi-index | 0.00 |
Reduction of chip packaging and cooling costs for deep submicron System-On-Chip (SOC) designs is an emerging issue. We present a simulation-based methodology able to realistically model the complex environment in which a SOC design operates in order to provide early and accurate power consumption estimation. We show that a rich functional test bench provided by a designer with a deep knowledge of a complex system is very often not appropriate for power analysis and can lead to power estimation errors of some orders of magnitude. To address this issue, we propose an automatic input sequence generation approach based on a heuristic algorithm able to upgrade a set of test vectors provided by the designer. The obtained sequence closely reflects the worst-case power consumption for the chip and allows looking at how the chip is going to work over time.