Efficient power co-estimation techniques for system-on-chip design

  • Authors:
  • Marcello Lajolo;Anand Raghunathan;Sujit Dey

  • Affiliations:
  • Politecnico di Torino;NEC, C&C Research Labs, Princeton, NJ;UC San Diego, La Jolla, CA

  • Venue:
  • DATE '00 Proceedings of the conference on Design, automation and test in Europe
  • Year:
  • 2000

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Abstract