Power analysis of embedded software: a first step towards software power minimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Energy characterization based on clustering
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Function-level power estimation methodology for microprocessors
Proceedings of the 37th Annual Design Automation Conference
Efficient power co-estimation techniques for system-on-chip design
DATE '00 Proceedings of the conference on Design, automation and test in Europe
JouleTrack: a web based tool for software energy profiling
Proceedings of the 38th annual Design Automation Conference
Instruction level power profiling
ICASSP '96 Proceedings of the Acoustics, Speech, and Signal Processing, 1996. on Conference Proceedings., 1996 IEEE International Conference - Volume 06
| Hi-index | 0.00 |
This paper describes a functionality-based instruction-level power analysis model, which aims at reducing workload of computing inter-instruction power and keeping the convenience to observe necessary parameters from a source-code description. The model treats the total power as the sum of basic power of individual functional component and switching power of consecutive components pairs. To get the switching power, the switching activities between two functional components are treated as one changing from working state to sleeping state and the other from sleeping state to working state. NOP instructions are used to model transitions between the two states. The model is experimentally validated on a wide range of embedded software routines. Experiments show that our model is within 95% accuracy on the average, and can reduce the workload from a complexity of O(n2), which is the workload of traditional instruction-level energy estimation techniques, to a complexity of O(n).